2. 18 .2 0 04 C8051F350 50 m i ps, 8 kb flash, 24-bit adc mcu prelimin a r y port 0 la tch uart 8kb y t e f l ash 25 6 b y t e sram por sf r bu s 8 0 5 1 c o r e ti me r 0, 1, 2, 3 3 - chnl pca/ wd t p 0 d r v x b a r res e t sy s t em clo c k digi t a l pow e r debu g hw sm bu s c2 d c2 d cp 0 + - cp 0 + p0.0 p0.1 p0.2 /xtal1 p0.3 /xtal2 p0.4 /tx p0.5 /rx p0.6 /cnvstr p0.7 vdd gnd /rs t/c2ck brow n - ou t 24 -b it a dc0 a m u x ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 vref+ 51 2 b y t e xr a m spi bus p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4 /cp0a p1.5 /cp0 p1.6 /idac0 p1.7 /idac1 cp 0 - 8-b i t ida c 0 8-b i t ida c 1 port 1 la tch vref pg a ana l og pow e r av+ agnd vref- te m p sensor b u ffe r + + of fset da c p2.0 /c2d port 2 la tch cp 0 a xt al 1 xt al 2 ex t e r nal osci lla tor cir c uit 24 .5 m h z 2 % inte rn al o s c ill at or clo c k m u lt ip lie r anal og p e riph era l s 24-bit a d c - no missing codes - 0.002 % no nli n earit y - programm abl e conversi on rat e s up to 1 ksps - 1x to 128x pga - 8 inp u t multipl e xer - built-in tem per ature sens or t w o 8-bi t cu rren t d a c s co mp arato r - programm abl e h y ster esis an d respons e time - confi gura b l e a s w a k e -u p or reset source - lo w curr ent (0.4 a) on-c hip d e bu g - on-chip d e b u g circuitr y faci lit ates full spe ed, non- intrusiv e in-s y s tem debu g (no emulator re qui red) - provid es break poi nt s, singl e steppi ng, w a tc hp oints - inspect/modif y memor y , re gist ers, and stack - super ior perfor m ance to emu l ation s y stems usin g ice-chip s, target pods, and sock ets - lo w cost, com p lete d e ve lopm ent kit supply voltage ................. 2.7 to 3.6 v - t y pic a l o perati ng curre nt: 17 ma @ 50 mhz 16 a @ 32 khz - t y pic a l stop m ode curr ent: <0.1 a high- speed 8051 c core - pipe lin ed i n struction arc h it ect u re; e x ecutes 70% of instructions in 1 or 2 s y stem c l ocks - up to 50 mips throug hp ut w i t h 50 mhz cloc k - exp a n d e d inter r upt han dl er me mo ry - 768 b y tes (2 56 + 512) interna l data ram - 8 kb f l ash; in- s y s tem pro g ra mmable i n 51 2 b y te sectors digital p e ripherals - 17 port i/o; all 5 v tolerant w i t h hig h sink curr ent - enha nce d hard w a r e uart , spi, and smbus ? serial ports - t h ree gener al purp o se 1 6 -bit counter/timers - 16-b i t program mabl e count er arra y w i th thre e capture/com p a r e modu les, w d t - real tim e clock mode usi ng p c a or timer an d e x terna l cloc k source cloc k s o urce s - internal osc ill ator: 24.5 mhz, 2% accur a c y s upp orts uart oper ation - exter nal osc ill a t or: cr y s tal, rc, c, or clock (1 or 2 pin mo d e s) - 2x cl ock multi p l i er to achi eve 5 0 mhz intern al clock - can s w itc h bet w e e n clock so urces on-th e-fl y 32-pin lqf p package temperature range: ?40 to +85 c
smbus is a t r ade m ark of intel corp.; spi is a trade m a r k o f mo to ro la, in c. C8051F350 50 m i ps, 8 kb flash, 24-bit adc mcu prelimin a r y selected electri c al specifications t a = ?4 0 to +85 c, v dd = av+ = 3.0 v, v ref = 2.5 v external, pga gain = 1x, mdclk = 2.4 567 mhz, de cimation ratio = 1 920 unle ss oth e rwise sp ecifie d. par a mete r c o nditio n s m i n t y p m a x u n i t s glo bal ch ar a c teris t ics s u p p l y v o l t a g e 2 . 7 3 . 6 v supply cu rre nt (cp u activ e ) c l oc k= 50 mhz c l oc k= 1 mh z c l oc k= 32 khz ; v dd monitor enable d 1 7 0.5 16 m a ma a supply cu rre nt ( s hu td ow n) oscillator n o t runni ng; v dd monitor disable d 0 . 1 a clo ck f r eq ue ncy ra nge dc 50 mhz 24- bit a/d c o nver ter re solutio n (no mi ssi ng code s) 24 bits integral nonli nearity single-ende d mode differential m ode 1 5 p p m f s offset erro r 5 ppm g a i n e r r o r 0 . 0 0 2 % comm on mo de rej e ctio n ratio ( c m r r ) 1 1 0 d b powe r suppl y rejectio n, dc 8 0 d b powe r suppl y current 2 3 0 a 8- b i t c urren t - m od e d / a con v er ter s re solutio n 8 b i t s integral nonli n e a r i t y 0 . 5 l s b differential nonline a rity guarantee d monotoni c 0.5 1 lsb package information a a1 a2 b d d1 e e e1 - 0. 05 1. 35 0. 30 - - - - - - - 1. 40 0. 37 9. 00 7. 00 0. 80 9. 00 7. 00 1. 6 0 0. 1 5 1. 4 5 0. 4 5 - - - - - mi n (m m) nom (mm) max (mm) pi n 1 d e n ti fi e r a1 e b 1 32 e1 d1 d e a2 a C8051F350dk development k i t
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